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1. Introduction
2. OXIDATION PRE-LAB REPORT
3. Degrease tweezers and wafers
4. Remove native oxide
5. RCA Cleaning
6. Oxidation
7. PHOTORESIST 1 PRE-LAB REPORT
8. Vapor degrease the IC wafer and tweezers
9. PR 1 - Open Windows For First Diffusion
10. Boron Predeposition
11. Remove Borosilicate Glass
12. Boron Drive
13. PR 2 - Open Windows for Phosphorus Predeposition
14. Phosphorus Predeposition Diffusion
15. Remove Phosphosilicate Glass
16. PR 3 - Open Windows for Gate Oxidation
17. Gate Oxidation
18. Measurement of Oxide Thicknesses using the Ellipsometer
19. PR 4 - Open Contact Windows
20. PROCESSING REPORT
21. Aluminum Evaporation for Contacts
22. PR 5 - Define Metal Contact Areas
23. Anneal Contacts
24. Electrical Testing
25. FINAL REPORT
26. References

Introduction

The class will be split into three groups which will start at different stages of the fabrication and testing. On the fifth meeting of the semester, everyone could be at the same step and requiring the same piece of equipment. Fortunately, people work at different paces and will probably be staggered enough to minimize such "collisions". It will be in your best interest to come prepared to proceed as far as possible in the process each period.

Cleanliness is of utmost importance in the fabrication process. Contaminants introduced during the process can degrade or destroy device performance. Therefore, it is important that processing equipment or chemicals are never touched with the bare hands, (i.e., diffusion furnaces, push rods, boats, etc.). Not only do the bare hands contain dirt and oils, but also sodium which can easily destroy FETs. Always handle the wafer with clean tweezers. A good rule to remember is to never touch anything with your bare hands that will come in contact with the wafer.

Always consult the instructor if any mistakes are made in processing. Always consult your instructor at the beginning of the period for any special processing instructions. Often the instructor will call a short meeting at the beginning to make such announcements to everyone at once.

Photoresist should not be left on wafers overnight. Do not begin a photoresist operation unless you are confident you can finish it. At the beginning of the semester a PR patterning process will take a little over an hour. Later, it will go quicker.

Processing Overview

The first step will be to clean and oxidize a batch of wafers in a group of three students. The wafers will be referred to as the "IC wafers" in this recipe. A pattern will be etched through the oxide using Mask l and the Photo-Resist (PR) process outlined in the manual. The wafer will then be subjected to a boron ambient at high temperature so that the boron will diffuse into the N-type silicon through the holes in the oxide, forming P-regions on the wafer in those areas delineated by Mask 1. This diffusion is known as the predeposition or "predep" diffusion.

After the wafer has been suitably cleaned and excess boron removed, it will be subjected to another diffusion, called the redistribution or "drive" diffusion, this time without the boron source. The idea here is to redistribute the dopant such that its concentration is more uniform (with respect to depth). This diffusion will be made in an oxygen atmosphere so that another layer of oxide is grown simultaneously on the wafer to protect the P-regions.

After suitable cleaning, a second PR process using Mask 2 will be used to delineate areas which will be changed back to N-type by a phosphorus predeposition diffusion. The third mask will be used to remove oxide from the gate regions of the FETs so that a thin high quality gate oxide may be grown there.

Mask 4 will be used to cut holes down to the various regions through which metal contacts to the silicon surface can be effected. Aluminum will then be vacuum evaporated over the entire wafer, and a final PR process utilized to etch the contact pattern using Mask 5. Scale drawings of these masks are available for study in appendix I of this manual. The ECE344 homepage on the World Wide Web (http://fabweb.ece.uiuc.edu:1999/) contains an interactive image of the mask set, which can be very useful in exploring the various regions of the mask set.

Finally, you will form ohmic Al-Si contacts by annealing. This is a process in which the components of a system are heated to a temperature below the system's eutectic point. (The melting point of a given alloy of one substance in another depends upon the percentages of the materials present. That point on a phase diagram of temperature vs. percent of each parent material present where a temperature minimum occurs in the liquidus line is known as the eutectic point. The eutectic point for the Al-Si system is 576°C.) You will use a temperature of 500°C which permits the aluminum atoms to move around and spread more uniformly over the silicon surface. In addition, during annealing, the aluminum can diffuse into the silicon itself. Annealing is used instead of alloying (i.e., heating of the system to temperatures above the eutectic point) because experience in our lab has shown that alloying often has a detrimental effect on the resulting p-n junction diode characteristics.

The devices will then be tested, and operational chips noted for further testing.

Cleanroom etiquette

OXIDATION PRE-LAB REPORT

1. What are the purposes of the SC-1 and SC-2 solutions in the RCA standard cleaning procedure? Refer to the article by Kern in Appendix B of the paper version.
2. As an alternative to the RCA clean, a clean which uses a sulfuric acid-hydrogen peroxide solution followed by an HF step has been proposed. List 5 advantages of this substitution. (See Pieter Burggraaf's article "Keeping the 'RCA' in Wet Chemistry Cleaning" in the appendix B of the paper version.) (The ECE 344 recipe uses Sulfuric acid rather than Hydrochloric acid in the SC-2 solution.)
3. Refer to the oxidation step below. What gases are flowing during
• dry oxidation?
• steam oxidation?
4. In the steam oxidation, how is the steam produced? Why is there a flame?
5. Explain in general terms why different thicknesses of oxide give different colors. Why is it important to view samples vertically? (see Anner section 5.10)

Degrease tweezers and wafers

Remove native oxide

1. Perform a 30-sec oxide etch in the 50DI:1HF acid under the SC-2 hood to remove any oxide which may have been built up due to exposure to air.
2. DI rinse in the SC-2 DI rinse. Change the DI when you get a chance before using again later.
3. Spray rinse. Be sure to spray off any HF that may have gotten on the handle.

RCA Cleaning

The procedures are posted on the wet lab's acid hoods, so please do not take your lab manual or notebook into the wet lab. All you have to remember are the general steps which in this case are to degrease, remove native oxide, and RCA clean.  

Oxidation

1. After a careful review of the instructions regarding the furnaces given in appendix F of the paper version, a student should insert the wafers into the steam oxidation furnace (T = 1100°C) with nitrogen flowing.
2. One group member should be assigned to time-keeping and switching gases. This person should switch from nitrogen to pure oxygen once the wafers have reached the center of the hot zone. (The O₂ flow should be about 120 and the N₂ should be off.) Then:
• After 10 minutes of O₂ (dry oxidation), turn on the hydrogen. ( You can see the glow from the flame produced by the combustion of H₂ and O₂ through the open end of the chamber. The H₂ flowmeter should read about 20.)
• After 10 minutes of steam (O₂ and H₂), turn off the hydrogen.
• 10 minutes later, switch back to nitrogen only.
3. A different student should remove the wafer boat.
4. Each student should remove one wafer and hold it in the air for 10 seconds before placing it into their wafer carrier. (The cool down time is essential to avoid melting of the wafer carrier!)
5. The time keeper should place the boat back into the furnace. Everyone should get some experience handling the quartzware. Further practice is also encouraged. Later on, you'll be doing things on your own without the 1:3 teacher student ratio so take advantage of the instructor now.

Starting Material Information

Determine the background doping of the substrate and the epitaxial layer. Enter the background doping for the epi-layer in your electronic logsheet file at the first opportunity.
N = ____________ cm^-3 

PHOTORESIST 1 PRE-LAB REPORT

1. Draw a flow chart of the basic positive PR process used for opening windows in unpatterned oxide for ECE 344. This includes etching the oxide and removing the PR. Use concise descriptions or names for each significant step. Refer to Appendices C and G, and note that for the standard PR process you do not use step C.2.12, which is for image reversal. You will be using Acetone and the PR degreaser for PR removal. For those who do not know what is meant by a flow chart, an example is shown. Just enough detail should be included to allow you or some other ECE 344 graduate to reproduce the process a year from now without the benefit of the lab manual excerpts we post in the lab. For the amount of detail we are looking for, your flowchart should fit on one page. It should also contain three conditional loops. (For example, see the one below for PR residue.)

2. There are several steps in the process where oxide is grown on your wafer. In places on your wafer where the oxide is never etched, the oxide thickness will continue to increase with each new oxidation. Field oxide is oxide in the "field" in between devices on your wafer, where the oxide is never etched. It is, therefore, the thickest oxide on your wafer at any given time.

Read through all the processing instructions (from the initial oxidation to Electrical Testing) for the IC Fabrication Experiment, and use GT-4, 6, and 7 to determine the thickness and color of the field oxide at each PR step. Show your work and all references to graphs and tables. The surface plane of your silicon wafer is (100), so use the (100) curves. Note: If, for example, a dry oxidation step is off the chart you may assume its contribution is negligible. Such assumptions should always be clearly stated, however!
You may not have covered oxidation in lecture yet, so here is some help: The graphs show thickness as a function of time, given as (t+T). If there is already oxide present on your wafer before a certain oxidation step, "T" is the equivalent time required under the current oxidation conditions (temperature, steam or dry...) to give that oxide thickness. The oxidation step is of duration "t". To find the thickness after the oxidation step, you need to use t+T, and read the corresponding thickness off the appropriate curve.

Here's an example: Suppose that you are to do a 12 min steam oxidation at 1100 C, and there is already 0.19 micron oxide present. From the 1100 curve on GT.6, 0.19 micron corresponds to T = 8 min. (In other words, it is as if you have already done 8 minutes in steam at 1100 C to give you the 0.19 microns already present.) Then add t = 12 min to T = 8 min to get t+T=20 min. At t+T = 20 min, read the 1100 curve to get a final thickness of 0.34 micron. (Note that the value of T would be different for a different temperature, or for dry oxidation.)

For the IC fabrication "recipe" to be followed for your IC wafer, what thickness and color of field oxide will be present prior to each PR step (PR 1 through PR 5) during processing? Remember to show your work and all references to graphs and tables.

3. The photoresist is pink, so it helps to avoid pink oxide. Will the field oxide on your wafer ever be pink at the end of an oxidation step?
4. The test instruments in the lab are limited to 200V. Will the breakdown voltage of the field oxide (the oxide which is never etched) exceed this figure when you complete the processing of your devices? Assume that the oxide will breakdown in an electric field of 10⁷ V/cm (a conservative figure). Show your work.

Vapor degrease the IC wafer and tweezers.

PR 1 - Open Windows For First Diffusion

1. Follow the procedure for putting a patterned layer of photoresist on the wafer given in appendix C of the paper version. (For the basic positive PR process, the image reversal step C.2.12 is not used.) This basic process is posted in the PR room in the form of signs, so please do not take your lab manual or notebook into the wet lab area.
2. NOTE: You should use Mask # 1. Since there is no pattern on the wafer already, you need not -and should not- waste time looking through the mask aligner microscope. Visually center the pattern with the wafer flat parallel to the bottom row and expose it with an 125mW-sec/cm² dose of ultraviolet energy. The UV intensity (mW/cm²) will be posted for each aligner. You are to calculate the time required.
3. Etch the oxide using 6NH₄F : 1HF (hot oxide etch) for 2.5 minutes. Slowly rotate the wafer carrier back and forth during the etch. Do NOT splash! Rinse in DI water thoroughly, and N₂ dry. (The 6:1 etch is called "hot" because it is stronger than a standard 10:1 etch. It is not actually hot in terms of temperature.)

Wet etching requires the diffusion of the etchant to the surface and the diffusion of the reaction products away from the surface. The smallest windows on the wafer will etch at rate closer to that of the large test areas with a little rotational agitation.
When coming out of the etch it is important to let the wafer carrier drip for a few seconds while no more than a few centimeters above the acid. Tilting the carrier in two opposing directions also helps return more acid to it's container. This not only keeps the DI rinses cleaner, but also minimizes the depletion of the acid container.
4. Use the hot point probe (see Appendix D) in the upper right window of the test areas to check for complete oxide removal. If no definitive reading (a few nanoamps or more) is obtained, etch in 30 second intervals until oxide is removed. Do not etch for more than 4 minutes without consulting your instructor.

 

 
5. Always follow up with a microscope inspection to insure that ALL the windows to be opened through the oxide are indeed etched to bare silicon. The test area should be uniform in color (dull silver) and all the windows should match it.
6. Record the wafer type (p or n) determined using the hot point probe.

Type = ________.
7. Initial PR Removal: Hold your wafer level over the waste acetone/IPA container (with the lid off) and squirt acetone on the wafer until it begins to flow off the edges. Let it dissolve the PR for 10-15 seconds before tossing the acetone into the waste container. Repeat until most of the PR is gone.
8. Strip off any remaining PR residue by degreasing the wafer in the old degreaser dedicated to PR removal duty.
9. Inspect the wafer under a microscope for PR residue. Go back into the degreaser if necessary. The clean wafer carrier may be used this time. Incomplete photoresist removal is the most common cause of furnace tube contamination. Please inspect wafers thoroughly.

Boron Predeposition

1. Clean the wafer in the vapor degreaser.
2. Perform a 10-15 second etch in 50:1 DI:HF if it has been more than an hour since opening the diffusion windows, DI rinse, and N₂ dry.
3. Have your instructor check the boron predep furnace and support equipment (i.e., gas flows). The boron predep furnace should be at 950°C.
4. Follow the procedure for furnace loading in appendix F of the paper version. Use the Boron predep furnace and load the wafer so that the patterned side is facing the nearest BN wafer. Be sure to record which position your wafer is in.
5. After a 15 minute predeposition at 950°C, unload your wafer.
6. Use the Veeco four point probe to get a rough idea of the sheet resistance. Consult the instructor if it's outside the range 80-160 ohms/square, you may have to return the wafer to the furnace. Note: The correction factor was determined for the smaller of the four point probe windows (upper left window below). Be sure "auto-penetrate" is on. If the Veeco reads that the conduction type is still N, then verify it with the hot point probe. Trust the hot point probe more.

R_s=__________ ohms/square.

Remove Borosilicate Glass

1. Clean the wafer for the drive diffusion and testing using the following procedure. (The idea here is to remove the borosilicate glass and any elemental boron formed on the wafer surface during predep.) The original thermally grown oxide is not removed, but it is etched slightly.
• Remove the borosilicate glass by placing the wafer in the 50:1 DI:HF oxide etch for 20 seconds. Follow with a thorough DI rinse.
• Immerse the wafer in 1 H₂SO₄ : 1 HNO₃ for 10 minutes to oxidize the elemental boron.
• Rinse thoroughly with DI water and return to the 50 DI:1 HF oxide etch for another 10 seconds to remove the oxidized boron.
• Wash very thoroughly in DI water and dry carefully with N₂.
2. Perform a hot-point probe measurement on any open region in the test area of the wafer. Record whether it is P or N type. (Refer to Appendix D in the paper version.) Also, make sheet resistance measurements on the wafer with the four point probe as before. Consult Appendix E in the paper version if necessary.
• Boron predep. Type ____________ R_s1 = ____________ ohms/sq.
• Enter your Rs value and furnace boat position into your electronic logsheet file ASAP.
• The sheet resistance after the boron predep should be between 75 and 150 ohms/square. If the measured value is out of this range consult your instructor. He or she may have you return your wafer to the boron predep furnace for an additional 10 minutes depending on the how far it's off. If this is required, the subsequent borosilicate glass removal times may be reduced proportionately.
• Did the Boro-silicate glass affect the four point probe measurement?

Boron Drive

1. Have your instructor check the boron drive furnace and support equipment (i.e., gas flows). The furnace should be at 1100°C.
2. Degrease your wafer using the instructions in Appendix B of the paper version.
3. Insert wafer into boron drive furnace using Appendix F of the paper version as a guide.
4. Perform the following drive recipe at T = 1100°C. (40 minutes total drive time).
• Dry oxygen drive for 15 minutes.
• Steam drive for 15 minutes.
• Back to a dry drive for 10 minutes.

PR 2 - Open Windows for Phosphorus Predeposition

Light field masks, being mostly clear, are easily aligned with the underlying wafer, but for masks 1 through 4 a negative PR must be used. For these steps we need the relatively sparse chrome regions transferred to the wafer as openings in the PR. With AZ5214 PR this image reversal is possible, but it is a more complicated process and sensitive to more variables. See appendix C (PR processing) of the paper version.

Most students will find it best to use the dark field versions of masks 1 through 4 and to use the light field version of mask 5. Why is mask 5 different?

1. Use the photoresist process to transfer the pattern from mask 2 into the oxide. Note that this time there is a pattern to which to align. Use an oxide etch time of 3.5 minutes before checking with the hot point probe for etch completeness. (Be sure to use the proper etchant solution for the oxide.) As in PR-1, expose the PR to an 125mW-sec/cm² dose of ultraviolet energy. Don't forget to complete the pattern transfer by removing the PR (as stated in Appendix C of the paper version).

The hot point probe measurement should always be done in a region of the test area which originally had the thickest oxide to be etched. There are two oxide thicknesses present on the wafer at this point. For subsequent mask layers there will be a larger number of various thicknesses.
The hot point probe measurement alone is NOT a sufficient condition to stop etching. The wafer should always be inspected under a microscope (preferably without filtered light.) Check many places on the wafer to verify that all the windows which are supposed to be open are uniform in appearance and identical in color to the hot point probe test area for that layer. Of course, the inspection requires familiarity with the mask set. Study the mask set so you know what to expect.
2. Measure the sheet resistance of the boron diffusion with the four point probe using the lower left window just opened for the phosphorus diffusion. You may ignore the fact that a slightly different correction factor should be used because this boron tub is 200 microns larger on a side. The larger size should result in a smaller measurement, but you will actually get a reading which is approximately double the previous measurement. Why?


Wafers with PR on them should NOT be probed with the four point probe. Poor aim can render the tips insulating and thereby yield false results to several students.

Phosphorus Predeposition Diffusion

1. Degrease one more time and inspect carefully for complete PR removal. Contamination of the furnace can affect more than just your wafer. In addition to the wafers of innocent students, there is over $1000 worth of quartzware and source wafers which could be ruined.
2. If it has been more than an hour since opening the diffusion windows, perform a 10-15 second etch in 50:1 DI:HF, DI rinse, and N₂ dry.
3. Perform a phosphorus predeposition diffusion at 1000°C for 10 minutes. Flow nitrogen at the standby rate for the first 5 minutes, then switch on the oxygen for the remaining time. Leave the nitrogen on the entire time. A low oxygen concentration (~5%) is used in order to minimize the phosphorus silicide formation described in 7.12 of Anner. The contribution to the field oxide thickness may be ignored for prediction purposes. Record the actual flow rates in your electronic logsheet.

It is always important to leave the furnace endcaps loose so they won't get stuck, but it's especially important on the Phosphorus furnace. You will find what is called a condensation tube attached to this endcap which minimizes condensation of P₂O₅ on the ground joint surfaces, but even with that it still gets stuck easily because of condensation. Be sure to use the special holder for the tip of the condensation tube when you place the endcap on the counter. It's just a U shaped piece of quartz, but it keeps the tip clean and prevents rolling.
4. Use the Veeco four point probe to get a rough idea of the sheet resistance. Consult the instructor if its outside the range 15-35 ohms/square. Be sure "auto-penetrate" is on and use the correct test area. Don't worry if the N and P lights flash - the Veeco cannot reliably determine the type for your wafer's surface concentration.

R_s= _________ ohms/square.



Which area should you use?

Remove Phosphosilicate Glass

1. Phospho-silicate glass is supposed to be considerably easier to remove than boro-silicate glass, but we'll use the same procedure to remove it. High surface concentrations of phosphorus are detrimental to photoresist adhesion so it is imperative that we remove it all.
• Remove the Phospho-silicate glass by placing the wafer in the 50:1 DI:HF oxide etch for 20 seconds. Follow with a thorough DI rinse.
• Immerse the wafer in 1 H₂SO₄ : 1 HNO₃ for 10 minutes.
• Rinse thoroughly with DI water and return to the 50 DI:1 HF oxide etch for another 10 seconds.
• Wash very thoroughly in DI water and dry carefully with N2.
2. Re-measure the sheet resistance. Did it change? Enter it in the electronic logsheet and "submit" the file ASAP.

R_s= ________ ohms/square.

3. Use the hot point probe to verify that the largest test area (on left) has indeed been changed back to N-type. Consult your instructor if it did not.

PR 3 - Open Windows for Gate Oxidation

Gate Oxidation

1. Degrease your wafer before this critical step. If we were going to employ one more RCA clean in this process, this is where it would be. Due to time constraints, we shall forego the more thorough cleaning.
2. Grow 250 Å of dry oxide at 1000°C in the newly opened windows. Use the gate oxidation furnace. It's up to you to calculate the oxidation time. Use the <100> curve to figure out the necessary oxidation time. Check that the O₂ flow = 100. If it is not, notify your instructor. (During the oxidation, take the opportunity to familiarize yourself with the workstations and/or fill in your logsheet file.)

Ellipsometer Measurements

PR 4 - Open Contact Windows

1. Use the standard photoresist process to transfer the pattern from mask 4 into the oxide. Use an oxide etch time of 3.75 minutes before checking with the hot point probe for etch completeness. As in PR-1, expose the PR to an 125mW-sec/cm² dose of ultraviolet energy. Don't forget to follow- up with a thorough microscope inspection. An incomplete etch here may result in device failure, particularly in the schottky diodes so check them carefully. A short 15-30 second overetch after a positive inspection will help ensure good contacts.
2. Measure the sheet resistances of the phosphorus and boron diffusions with the four point probe.
• R_s(Boron)= ________ ohms/square.
• R_s(Phos.)= ________ ohms/square.

Processing Report

(Hints here)

1. Use Difcad 2 to help construct a band diagram of your vertical BJTs at equilibrium. Show the collector and emitter contacts (and everything in between) in the diagram. You may neglect showing the base contact because it cannot be elegantly presented in the same band diagram. Calculate the energy levels at several points in each region of the structure. Note that DIFCAD will only give you the net doping profile. You must use that information to calculate the energy bands. This can easily be done by adding a few columns to the DIFCAD Excel spreadsheet, but be careful about depletion regions! They are not so easily included.
2. List ALL the processing reasons (other than contamination) you can think of that may cause the real energy bands in your fabricated device to be different from what you determined above. Understanding the limitations of the theories you use is almost as important as the theories themselves. For each of the processing steps, think about what actually goes on, but is not included in your DIFCAD calculations. (For example, why is the base doping profile not the same as what is calculated in DIFCAD?)
3. Draw the cross section of one of your P-channel FETs. Include all significant regions while the device is biased in saturation. Your diagram should show at least the following items:
• lateral diffusion of dopants
• diffusion depths
• the channel
• depletion regions
• varying oxide thicknesses, labeled with thicknesses
• height variations of the silicon surface, due to consumption during oxidation
• some idea of lateral dimensions

The horizontal and vertical scales should not be the same. Why? You may use the (100) oxidation curves or oxide thicknesses measured using the ellipsometer. Be sure to state whether you are using the measured or calculated thicknesses.

4. Draw a detailed cross section of one of your BJTs unbiased and at equilibrium. Be sure to state whether you are using the measured or calculated oxide thicknesses. Your diagram should show at least the following:
• lateral diffusion of dopants
• diffusion depths
• depletion regions
• varying oxide thicknesses, labeled with thickness
• height variations of the silicon surface, due to consumption during oxidation
• some idea of lateral dimensions

 

5. The ECE 344 recipe compromises the performance between the three main transistor types. In this question, you will explore the effects of processing parameter changes on the performance of the different transistor types present on your wafer:
• Construct a table like the one below. Fill in the table by listing the effect that each processing step has on the physical device parameters (after all processing is completed), where xjC and xjE are the junction depths of the collector/base and emitter/base junctions, respectively, Wb is the base width, and Ci is the capacitance of the insulator in the gate of the FETs. Note that some steps will not affect some parameters.
 
• Construct a second table like the following one. Fill in this table by listing the effect that each physical device parameter has on the electrical performance characteristics of the device (like Beta, Vt...). (Note: an N-channel MOSFET has an n-type source and drain.)
 
6. Use your tables from above to aid in determining specific changes to the recipe you would make in order to improve the performance of each type of transistor (e.g. increase time of _____ in order to....) (These should be changes to the processing parameters only, not to the mask layout.) Do not specify processes which you cannot perform in the ECE 344 facility (e.g. ion implantation). Specifically:
• What change(s) would you make to improve the performance of the npn BJTs, and how will that affect the performance of the P-MOSFETs and N-MOSFETs.
• What change(s) would you make to improve the performance of the P-MOSFETs, and how will that affect the performance of the N-MOSFETs and npn BJTs.
• What change(s) would you make to improve the performance of the N-MOSFETs, and how will that affect the performance of the P-MOSFETs and npn BJTs.
7. The ECE 344 device layouts compromise the performance of the three main transistor types for the sake of processing tolerance. For each type of transistor (NPN BJTs, N-MOSFETs, and P-MOSFETs) describe or illustrate a single change to the layout you would make in order to improve its performance in some way. Briefly discuss the ramifications of your proposed changes if they were implemented (e.g. less misalignment tolerance). Look closely at the device cell mask set in Appendix I.
• BJTs: (Hint: The distance between contacts is relatively large. What does that do to device performance? How could you change the layout to improve the performance. What effect does that have on processing tolerance?)
• P-MOSFETs: (Hint: The gate oxide and metal overlap the Source and Drain regions. What does that do to device performance? How could you change the layout to improve the performance. What effect does that have on processing tolerance?)
• N-MOSFETs

Aluminum Evaporation for Contacts

Consult your instructor before attempting the metal lift-off process. If you do the liftoff process, be sure to follow the PR recipe for liftoff in Appendix C of the paper version of the lab manual. Otherwise, proceed with the standard etch back technique described below.

1. Degrease if surface contamination is suspected.
2. If more than an hour has passed since PR-4, remove the native oxide with a 10-15 second dip in the 50:1 DI:HF, DI rinse, and N₂ dry.
3. Bake out moisture on the bakeout hotplate for 1 minute. (Wafer must be completely dry and clean.)
4. In the Cooke evaporation system, place 3 pre-cut 3cm Aluminum wires in the tungsten filament, load the wafer into the holder directly above the aluminum (pattern side down), manually pump down and evaporate all the Aluminum as per Appendix A in the paper version. Do not use the filaments in series. Approximately 1500 Å will be deposited.
5. Vent and remove wafer for inspection.

PR 5 - Define Metal Contact Areas

1. Transfer the pattern from the final mask to a layer of PR using the standard PR process one more time. After spinning, the PR is not as easily seen on top of the aluminum as it has been in previous steps. As in PR-1, expose the PR to an 125mW-sec/cm² dose of ultraviolet energy.
2. Etch in the Al etch [1 H₃PO₄ : 1 HN0₃ : 1 DI] for 30 seconds AFTER the pattern looks visually complete (5 - 10 minutes). You do not need to take the wafers out of the etch to check for completeness. Position the wafer/carrier so you can see the patterned side change from a mirror to a superposition of the mask 5 pattern on the pre-aluminized wafer. It will be obvious what is meant by "visually complete." 1500 Angstroms of aluminum looks just like 150 - it's a mirror! The extra etch time is because the last few monolayers of aluminum will look invisible yet they can carry undesirable electrical currents.
3. Remove the PR as usual.

Anneal Contacts

1. Adjust N₂ flow to 10 on the flowmeter if it is not there already.
2. Load your wafer into the annealing furnace for 15 minutes at T = 475°C.
3. When the 15 minutes have elapsed, remove the wafer from the furnace and place it in your wafer carrier. Be sure that the boat pushrod is fully inserted into the quartz tube so that it will not be broken. Return the empty boat to the front of the furnace tube.

Electrical Testing

Review appendix J in the paper version for tips on the proper operation of the probers. Refer to the World Wide Web pages http://fabweb.ece.uiuc.edu:1999/Software/UNIX for help in using the UNIX workstations and http://fabweb.ece.uiuc.edu:1999/Software/ICCAP for help with IC-CAP, the Integrated Circuit Characterization and Analysis Program.

There is also information there about

• which BJTs to test
• which FETs to test,
• which Capacitors to test,
• which Diodes to test,

Understand and fill in each data set in the my_models.mdl model file with data from 3 of each device type. The three types of FETs it takes to fill in one model are sufficient for the first round of testing.

Outside of the lab, perform the extractions, simulations, and optimizations described in the ICCAP instructions.

One part of the measurement setups not covered well in the ECE 340 text are the gummel plots for the BJTs.

Gummel plots are simply the display of the natural log of base and collector currents as Vbe and Vce(=Vbe) are varied simultaneously . The collector and base potentials are kept identical and the currents measured independently as the emitter potential is swept. The base current will display the characteristic regions of thermal recombination-generation dominance at low currents (I=I_o e^(qV/2kT)), quasi-ideal (I=I_o e^(qV/kT)), and current limiting ohmic effects at high currents. The corresponding collector current through these ranges can tell a lot about how useful the BJT will be for certain applications. The ratio of the two currents, beta, will usually have a peak somewhere in the middle, the broader the better. It can tell the circuit designer how sensitive the device is to the bias point.

The additional advanced testing will be handled using a handout when it seems clear just how much time will be available.

FINAL REPORT

NOTE: In this report, as in any engineering level report, state your assumptions clearly. Making reasonable assumptions is OK, but you must clearly state and justify them. Full credit cannot be given in cases where, say, the voltage reference direction is important, but not stated. Pictures often help in clearing up such ambiguities. Device location information is also important if verification of results is to be possible. Show all work in the written report.

This report will be submitted partially in electronic form. No printouts of the ICCAP files or your logsheet file will be necessary except for your own benefit. In the questions that ask you to generate plots in ICCAP, be sure to save the plots in your my_models.mdl file. After completing the items below, you are to submit your data files to your instructor's directory using the program called "submit." The syntax is:

submit <filename> to <instructor's login name>

Even if your wafer didn't work or work completely, still do the best you can with answering the questions and completing the tasks below. We can't give partial credit for answers like "my BJTs didn't work".

1. ELECTRONIC-LOGSHEET: Enter or verify all the process variables in the file logsheet and submit it one last time. In your lab notebook, enter any observations and conclusions you can make from the data. The size of the file is meant to impress you with the large number of process variables involved in our greatly simplified IC process. Do not make up numbers if you missed collecting some of them. The data will be used some day to demonstrate Statistical Process Control concepts. The deadline for submission may very well be earlier than the written part of the report.

submit logsheet to <instructor's login name>
2. After fabrication of your FETs, the actual gate lengths are shorter than the designed gate lengths as drawn using the CAD system. The diagram below shows the designed gate mask and the gate region of one of your diffused p-channel FETs. The designed gate width drawn on the CAD system is L, and L-DL is the final (actual) gate length. (Note that the designed mask is not necessarily the same as the actual mask.
 
• Think about all of the steps that come between designing a mask using a CAD system and the final (diffused) device. Why is the actual gate length shorter than the length in the CAD drawing for the mask? (i.e., what causes DL?) There are several contributing factors.
• What happens if DL is greater than L? How does that show up while testing the device?
• What was the shortest gate length device that worked on your wafer? What upper bound does that place on DL? What is a reasonable lower bound?
• For two FETs in the same device cell, nearly the same amount (DL) is subtracted from the gate length for each device. In other words, DL does not depend on L. It is possible to determine the discrepancy between the actual and the as designed channel lengths from measurements of two different FETs. Create plots (in ICCAP) of gm (transconductance) vs. vg in the large and short FET setups. Use a transform to do the derivative (i.e., to calculate gm). The slopes of the gm curves in the saturation region are functions of the channel lengths. (Be careful about what the saturation region is!) The relationships may be found in section 8.3.5 of Streetman. Find DL.
3. Ideality factor of diodes:
• Create a plot called ideality in the Ifwd_vs_V setups of the diodes_344 models (and/or its copies) to plot the ideality factor, n, from equation 5-71 in section 5.6.2 of Streetman:

,where V is the voltage across the junction, I_o is the reverse leakage current, and n is the ideality factor.
Plot n vs. current. Use GT.19 for the value of kT/q. I_o may be taken as the leakage current with a reverse bias of 1 volt (read it off your breakdown plot). Use the functions in the functions list to enter the expression for n into the Y-data of a plot. Plots can be copied between setups by specifying the "path" to the target setup in the new name (see upper left of setup) or by writing them to a file and reading them in from the other setup.
• Why shouldn't you plot the ideality factor vs. voltage? (There is a practical reason related to the way testing is done. Try it if it is not immediately obvious).
• The voltage you measured for your diode includes the series resistance of the contacts and the n and p-type material on each side of the junction in addition to the voltage across the junction itself. The voltage used in equation 5-71 of Streetman should be only the voltage across the junction, whereas the entire measured voltage was used in the plot you created. Make a correction to the equation to take the series resistance into account. The forward series resistance of your diode can be determined from the slope of the I-V curve in the linear, high-current region. For each diode, use the value of the resistance to make a new plot called ideality _corrected, which plots the ideality factor vs. current, eliminating the voltage due to series resistance.
 
• What effect does correcting for the resistance have on your ideality plots?
• What is the effect of using a smaller value for Io in your ideality plots?
• What do expect to see in the ideality plots (see Streetman)? Do you see it?
4. For a one-sided step junction, the junction capacitance is given by

, where A is the area, V is the applied voltage (V < 0 for reverse bias), and N is the doping on the lighter-doped side.

For a one-sided junction with linear grading on the lighter-doped side, the junction capacitance is given by
, where G is the grade constant (slope of N at the junction). (See Streetman.) Real diffused junctions are somewhere between these two cases.

• What should the slope of a log(C) vs. log(V_o-V) curve be for a one-sided step junction?
• What should the slope of a log(C) vs. log(V_o-V) curve be for a one-sided junction with linear grading?
• For each C-V plot of the pn junctions (in diodes_344.mdl and/or its copies), plot log10(C) vs. log10(V_o-V) using ICCAP, where V is referenced as a positive voltage under forward bias. Refer to the band diagram in your Processing Report to make an initial guess for Vo. Improve your estimate for the built-in voltage for each pn junction by extrapolating a plot of C^(1/slope) vs. V to the x-axis, where "slope" is the slope in the high voltage region of your first plot. Use ICCAP to generate and fit the plot. Plug the new value for Vo back into the first plot and iterate this process until you get the same value out of the second plot (within a few percent). Note: if you cannot reasonably fit a line to the entire voltage range, use the high voltage regions.
• Compare the slopes of your log(C) vs. log(V_o-V) curves for the emitter/base and collector/base junctions. What does this say about your junctions? Is it what you would expect?
5. Submit my_models.mdl to your instructor using the submit command after all the plots requested above are included. The deadline for this may be before the written report.

submit my_models.mdl to <instructor's login name>
 

6. Capacitor breakdown: Determine the breakdown field of the capacitors from your measured breakdown voltage and the oxide thickness. Use the oxide thickness as determined in the following three different ways. Discuss any discrepancies between them. Use the oxide thickness:
• predicted by the appropriate oxidation curves,
• determined by the ellipsometer measurement, and
• calculated from your measured capacitance vs. voltage curves.
7. There is a great deal of information contained within your measured capacitance vs. voltage curves. In this question, you will extract some of the information, including the doping level of the silicon epi-layer. See Streetman section 8.3.2 or any other reference concerning MOS capacitors. (Note that in this question, the capacitances are NOT per unit area, as they are in Streetman.) You can find information about the capacitor area by using the interactive mask set on the ece344 WWW home page.
• What is your measured value of the insulator capacitance, Ci?
• What is your measured value of the total capacitance, Cmin, when the capacitor is biased such that the depletion region is at maximum width?
• What is happening in the portion of the C vs. V curve where C is not constant? (i.e., what is changing in the device that causes the capacitance to vary?)
• From your values of C_i and C_min, what is the value of the depletion capacitance, C_d, when the capacitor is biased such that the depletion region is at maximum width?
• From Cd, what is the maximum depletion width, wm, of the capacitor?
• At what measured value of voltage does the capacitor reach maximum depletion width, and what parameter of an FET should that voltage correspond to?
• From the maximum depletion width, wm, find the doping concentration, Nd, of the silicon epi-layer.
• How would your measured C vs. V curve be different if:
• The epi-layer was p-type?
• the doping level was higher?
• the gate oxide was thicker?
8. How do the threshold voltages from the FET measurements compare with those from the capacitor B measurements? Which would you trust more?
9. Compared to the single diffused diodes you measured (C-B junction), what differences would you expect if you:
• used a substrate contact several device cells away?
• measured the round Schottky diode?
10. List all the effects you can think of which cause the geometry of the various regions of the final devices to differ from the CAD layout. (Note that not all of these reasons will be processing mistakes.)
11. DIODES: Compare the values of the built-in voltage obtained in the following three ways:
• Vo determined from your capacitance data (log[C] vs. log [Vo-V] curves.)
• Vo determined by extrapolating a line from the linear portion of the forward I-V characteristics of the junctions.
• Vo predicted by the BJT band diagram in your processing report.
• Compare and discuss ALL the possible reasons you can think of for discrepancies between the background doping levels determined from the manufacturer's stated value of the starting epi-layer resistivity and the capacitor measurements.

References

1. SUPPLEMENTARY REFERENCES ON OXIDATION.

M. Atalla, E. Tannenbaum, E. J. Scheibner, "Stabilization of Si Surfaces by Thermally Grown Oxides," Bell System Tech. J., 38, 749 (May 1959). (Same as Bell Telephone Monograph 3254, see especially pp. 15 and 16.)
E. Deal and A. S. Grove, "General Relationship for the Thermal Oxidation of Silicon," J.A.P., 36, 37770 (December 1965).
J. Frosch and L. Derick, "Surface Protection and Selective Masking During Diffusion in Si," J. Electrochem. Soc., l04, 547 (1957).
Burger and Donovan, Fundamentals of Silicon Integrated Device Technology, Vol. 1, pp. 93- 98.
Ghandhi, The Theory and Practice of Microelectronics, Ch. 6.
Glaser/Subak-Sharpe, Integrated Circuit Engineering, Section 5.6.
Anner, Planar Processing Primer, Ch 5.
2. SUPPLEMENTARY REFERENCES FOR 4-POINT PROBE MEASUREMENTS.

Anner, Planar Processing Primer, Sections 3.4 - 3.11.
Gibbons, "Ion Implantation in Semiconductors - Part I, Range Distribution Theory and Experiments," Proc. IEEE 56, (1968), p. 295.
Ghandhi, Chapters 4 and 5.
Bond and F. M. Smits, "Interference Microscope for Measurement of Extremely Thin Surface Layers," BSTJ, 35, 1209 (Sept. 1956). (Same as BT Monograph 3682.)
3. Metal-Semiconductor Systems

Biondi, Transistor Technology, 3, 1958, Chapter 7.
Warner and Fordemwalt, eds., Integrated Circuits, Design Principles and Fabrication, 1965, pp. 307-309.
4. P-N Junction Capacitance

SEEC, Vol. 2, Section 5.4, pp. 93-96.
5. Vacuum Technology

Van Atta, Vacuum Science and Engineering, McGraw-Hill.
Brunner and Batzer, Practical Vacuum Technique, Reinhold.
Guthrie, Vacuum Technology, Wiley.
6. Theoretical

Smits, "Formation of Junction Structures by Solid State Diffusion," Proc. IRE, 43, 1049 (1958). (Same as BT Monograph 3136.)
7. Diffusion

D'Asaro, "Diffusion and Oxide Masking in Si by the Box Method," S.S.E., 1, 3 (1960). (Same as BT Monograph 3704.)
ride as a Diffusion Source for Silicon," RCA Review, 28, 2, pp. 344-350 (June, 1967).
Anner, Planar Processing Primer, Chapters 6 and 7.

ECE 344 home page.

Processes/ece344.exp.html updated 2 Sept 97

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