Figure 5-1: DUTs and Setups for the MOSFET Model
This chapter contains step-by-step procedures for using the MOSFET model supplied with the IC-CAP system. It includes a description of model setup, instrument connections, and model parameters.
This chapter describes the UCB MOSFET transistor model supported in SPICE, and the techniques used to extract model parameters. Using the Model file named nmos2.mdl, this chapter provides step-by-step instructions for making DC and capacitance measurements and their corresponding extractions. You also can use the Model file as a template for creating custom Model configurations, which you can save under names of your own definition.
The UCB MOSFET model is fully compatible with the UC Berkeley model developed for use with the UCB SPICE simulator. The model is actually a combination of three models, each being specified by an appropriate value of the LEVEL parameter. After specifying the model, enter the correct set of parameters for that model. Some of these parameters are shared between different models, while others affect only a specific model.
The extraction for the LEVEL 1 model (Shichman-Hodges) is not supplied with this release of IC-CAP. The LEVEL 2 model [1] is an advanced version of LEVEL 1, and can use either electrical or process type parameters. The LEVEL 3 [1] model is semi-empirical because it uses parameters that are defined by curve fitting rather than by device physics.
IC-CAP provides four configuration files for the MOSFET model. Two files are provided for each level (LEVEL 2 and LEVEL 3), one for an NMOS device and one for a PMOS device. The provided file names are:
The model is supported by all SPICE simulators currently included with IC-CAP. These include the SPICE2, SPICE3 and HPSPICE simulators. The provided Model files can also be used with the HSPICE simulator, and, with some modification, the Saber simulator.
NOTE: The SPICE2, SPICE3, and HPSPICE simulators are provided with IC-CAP as a courtesy to the IC-CAP users, and are not supported by Hewlett Packard.
Note that the default nominal temperature for HPSPICE is 25 degrees C. For SPICE2 and SPICE3 it is 27 degrees C. To force a nominal temperature, set the TNOM variable under the Utilities menu to the desired value.
The procedures for extracting LEVEL 2 and LEVEL 3 parameters are similiar. There are differences in the parameters extracted and the extraction functions used, but the procedures are identical. The parameters extracted for each LEVEL are listed in table 5-2 (LEVEL 2) and table 5-3 (LEVEL3).
NOTE: The measurement of devices and the extraction of parameters have been described in a specific order: large device, narrow channel device, and short channel device. It is mandatory that these procedures be carried out exactly in the order described. If they are not, there will be erroneous results.
In general, the procedure consists of measuring the output of three devices:
The measurement on these three devices provides sufficient information for extracting a full set of model parameters, including the channel length and width dependence.
These devices are first measured, using individual Setups for each device named idvg. The short channel device is measured twice, the second time using a Setup named idvd.
With each of the three devices, using the appropriate DUT (large, narrow, or short), and Setup (idvg), measure the drain current (Id) as a function of gate voltage (Vg) for a series of different substrate voltages (Vb) at a low drain voltage (commonly, Vd = 100 mV). The device in this case is operating in the linear region.
The fourth Setup (idvd) is then used to measure Id as a function of Vd for a series of gate voltages. As previously noted, this measurement is performed only on the short channel device. This measurement provides the information in the saturation region, and is used to extract the saturation parameters.
After completing the measurement procedure, execute the extraction command on the same Setups.
In DC parameter extraction, the extracted parameters are directly related to the geometries of the devices being tested. For a DUT to accurately extract DC model parameters, it must have the correct L (drawn or mask channel length) and W (drawn or mask channel width) device parameters with which to work. Before executing an extraction or simulation, edit each DUT to make sure the L and W parameters are correct.
Before starting the extraction, enter several process parameters. The most important of these is TOX. Determine TOX by reading the process information for the device, or by measuring the oxide capacitance. The TOX parameter is measured in meters. Enter its value directly in the Parameter Editor, or run the init_parameters macro supplied with the nmos configuration files. Also use the init_parameters macro to enter initial values for XJ, LD and RS. These initial values can contribute to the accuracy of the extracted parameters. They are overwritten by new values when the XJ, LD, and RS are extracted during the extraction process.
The drain-to-substrate and source-to-substrate junction capacitances are modeled as a combination of the sidewall and bottom (area) capacitances. To extract the parameters for these capacitances, first measure capacitance against voltage on two different size capacitors. Then execute the extraction command using two Setups: cjdarea, and cjdperimeter. Execute cjdarea on a square shaped capacitance with a small sidewall to bottom ratio, and cjdperimeter on a long, narrow junction with a large sidewall to bottom ratio.
Each p-n junction should be reverse biased when measured. Extraction is performed by the MOSCV_total_cap function. The parameters CJ, MJ, CJSW, MJSW, and PB are calculated from a combination of the two measurements.
Before running the extraction, be sure to specify the area and perimeter of the capacitance. Enter these numbers by executing the init_cap_parameters macro. This sets the variables defined at the Model level for the area and perimeter of the two DUTs. The parameters AD or AS (area) and PD or PS (perimeter) in the cbd1 and cbd2 DUTs are set by these variables.
The UCB MOSFET Model consists of the parameters listed in table 5-1. The parameters are categorized in this table according to the DC and CV extraction in IC-CAP. Note that some of these parameters are redundant and therefore only a subset of them is extracted in IC-CAP. Table 5-1 contains the parameters for all three levels of the model. Table 5-2 lists only the LEVEL 2 parameters, and table 5-3 lists only the LEVEL 3 parameters. Tables 5-5 through 5-11 contain a more detailed listing and definition of these parameters.
Extraction routines are provided for Classical, Short-channel (including External Resistance), Narrow-width, Saturation, Junction Capacitance, and Sidewall capacitance parameters.
NOTE: As categorized in table 5-1, model and device geometry parameters are listed together. Device parameters are identified by an asterisk (*).
CONTROLLING MODEL PARAMETERS
PARAMETER TYPE Level 1 Level 2 Level 3
Classical parameters VTO,GAMMA,PHI NSUB NSUB
KP UO,UCRIT,UEXP,UTRA UO,THETA
IS,JS,TOX NFS,NSS,TPG NFS,NSS,TPG
Short-channel parameters LD,XJ LD,XJ
Narrow width parameters DELTA,WD
Saturation parameters LAMBDA NEFF,VMAX ETA,KAPPA
External resistances NRD*,NRS*,RD,RS
Junction capacitances AD*,AS*,CBD,CBS
CJ,FC,MJ,PB
Sidewall capacitances PD*,PS*,CSJW,MJSW
Overlap capacitances CGBO,CGDO,CGSO
General LEVEL,L*,W*
IC-CAP Temperature Specification TNOM (system variable)
Note: The level 1 parameters are also used in level 2 and level 3.
Table 5-1: Summary of UCB MOSFET Model Parameters
DUT SETUP INPUTS OUTPUTS TRANSFORM FUNCTION EXTRACTIONS
large idvg vg,vb,vd,vs id extract MOSDC_lev2_lin_large NSUB,UO,UEXP,VTO
optimize Same parameters
narrow idvg // // extract MOSDC_lev2_lin_narrow DELTA,WD
optimize Same parameters
short idvg // // extract MOSDC_lev2_lin_short LD,RD,RS,XJ
optimize Same parameters
short idvd vd,vg,vb,vs id extract MOSDC_lev2_sat_short NEFF,VMAX
optimize Same parameters
cbd1 cjdarea vb,vd cbd set_CJ Program initial zero bias CJ
extract Optimize CJ,MJ,PB
cbd2 cjdperimeter vb,vd cbd extract MOSCV_total_cap CJ,MJ,CJSW,MJSW,PB
Table 5-2: Setup Attributes for the LEVEL 2 Model
NOTE: The parameter WD does not exist in the UCB version of SPICE. Because it is quite important, it has been added to a number of existing versions of SPICE, and is included in IC-CAP as well. If WD does not exist in your simulator, ignore the result (set to zero), or subtract 2*WD from the channel width. In the MOS Model files provided with IC-CAP, the width specification W in each of the DUTs has been modified to subtract the value of 2*WD from the drawn width. The parameter WD is specified in the Model level Variable table.
DUT SETUP INPUTS OUTPUTS TRANSFORM FUNCTION EXTRACTIONS
large idvg vg,vb,vd,vs id extract MOSDC_lev3_lin_large NSUB,UO,UEXP,VTO
optimize Same parameters
narrow idvg // // extract MOSDC_lev3_lin_narrow DELTA,WD
optimize Same parameters
short idvg // // extract MOSDC_lev3_lin_short LD,RD,RS,XJ
optimize Same parameters
short idvd vd,vg,vb,vs id extract MOSDC_lev3_sat_short ETA,KAPPA
optimize Same parameters
cbd1 cjdarea vb,vd cbd set_CJ Program initial zero bias CJ
extract Optimize CJ,MJ,PB
cbd2 cjdperimeter vb,vd cbd extract MOSCV_total_cap CJ,MJ,CJSW,MJSW,PB
Table 5-3: Setup Attributes for the LEVEL 3 Model
This section describes the general procedure for extracting model parameter data from the UCB MOSFET. The procedure applies to all types of parameters. The differences between extracting one type and another lie primarily in the types of instruments, Setups, and Transforms used.
Parameters are extracted from measured data taken directly from instruments connected to the inputs and outputs of the DUT. Simulated data may be generated by the simulator, using the extracted parameters. After both measured and simulated data have been acquired, each data set can be plotted and the resulting Plots visually compared in the Plot Window.
IC-CAP also extracts model parameters from simulated data. This capability is useful for creating a set of model parameters from the parameters of another model (parameter conversion) or for testing the accuracy of the extraction.
When performing an extraction, accurate results depend on the sequence of the steps followed. It is extremely important to follow the DC extraction sequence exactly as it is described below. It is also important to remember to enter the L (length) and W (width) device parameters in the DUT Parameter Table for each DUT as accurately as possible.
Capacitance parameters may be extracted before or after the DC parameters. The extraction requires that two different DUTs be measured. The model parameters are extracted from the second DUT.
Starting with the measurement process, the general extraction procedure consists of the following steps:
Install the device to test in a test fixture and connect the required test instruments.
Make sure the test fixture, signal source and measuring instruments, and workstation are physically and logically configured to the IC-CAP system.
This completes the procedure. By selecting the proper DUT and Setup, you can measure and extract parameter data of any device.
This section lists the instruments to use for measuring the characteristics of MOSFET transistors. For more detailed information, refer to chapter 11, Measurement.
DC model parameters are derived from measured DC voltage and current characteristics, using the HP4141, HP4142, or HP4145.
Capacitance model parameters are derived from measured capacitance characteristics at the device junctions, using the HP4271, HP4275, HP4280, HP4284, or HP4194.
Install the device in a test fixture. Verify the identity of device nodes and connect the required SMUs to the DUT. Refer to the Setup tables for the correct connections.
Table 5-4 is a cross reference of the connections between the terminals of a typical MOSFET device and various measurement units. These are the connections and measurement units that are defined in all four of the Model configuration files ( nmos2.mdl, pmos2.mdl, nmos3.mdl, and pmos3.mdl ), and can be modified.
The Inputs and Outputs in the various Setups use the following abbreviations for the MOSFET device nodes:
These nodes are defined in the Circuit Editor and can be modified. The measurement units, which also can be modified, are defined in the Hardware Editor table, with the following abbreviations:
In table 5-4, DUT is the name of the DUT as specified in the DUT-SETUP tile. DRAIN, GATE, SOURCE, and BULK are the names of the transistor terminals. As an example of how to read the Table, the first line indicates that DUT large has the DC measurement unit SMU1 connected to its source, SMU2 connected to its gate, SMU3 connected to its drain, and SMU4 connected to its bulk.
DUT DRAIN GATE SOURCE BULK COMMENTS large SMU1 SMU2 SMU3 SMU4 narrow SMU1 SMU2 SMU3 SMU4 short SMU1 SMU2 SMU3 SMU4 cbd1 CM(L) open open CM(H) calibrate for parasitic capacitance cbd2 CM(L) open open CM(H) calibrate for parasitic capacitance
Table 5-4: Instrument-to-Device Connections
The following section includes the recommended steps for measuring and extracting model parameters from a typical MOSFET transistor.
In this example, you read in the nmos2.mdl Model file, perform measurements and extractions, and save the completed Model to a name you define. All measurement and extraction functions are performed from the Model Editor, using the Setup names in the DUT-SETUP tile. The instructions assume that IC-CAP is running. If it is not, refer to chapter 3, Startup and Operation. This procedure extracts LEVEL 2 parameters from an NMOS device. To extract LEVEL 3 parameters, load nmos3.mdl. To extract the parameters from a PMOS device, use pmos2.mdl and pmos3.mdl.
In summary, you execute the following procedures:
NOTE: For accurate results, extract the MOSFET DC parameters exactly in the order specified in the instructions. The measurements, however, may be done in any order.
/usr/iccap/data
This sets IC-CAP to the directory that contains the nmos2.mdl Model file.
A Dialog Box showing all *.mdl files will be displayed.
Move the mouse pointer to the line that contains nmos2.mdl and click LEFT.
This selects the file and places its name in the Selection field at the bottom of the Dialog Box.
It takes several seconds to read the file and configure IC-CAP.
When complete, the nmos2 Model Editor appears. You are now ready to begin measurement and extraction operations.
When working with the MOSFET model, remember these two points:
This assures accuracy, since the parameter extractions are dependent on each other. Do all of the measurements, followed by all of the extractions, and finally, the simulations. Extraction usually provides a reasonable fit to the measured data, but you may optimize the data to attain an increased level of accuracy. Execute the optimization after extracting the DC parameters for each Setup. Optimization is usually not required for capacitance data.
value - 2 * WD
where value is the drawn width W, and WD is the parameter defined as one of the Model variables.
This completes the DC measurements.
Perform the model parameter extractions as follows:
Drag the pointer to Extract and release the mouse button to extract the LEVEL 2 Classic parameters.
All DC model parameters have now been extracted and their values placed into the Parameter Editor. To view these values, move the mouse pointer to the Parameter Set title on the Model Editor title bar, press LEFT to display the pulldown menu, drag the pointer to Edit, and release the mouse button. A list of the extracted model parameters appears in the Parameter Editor.
Figure 5-1: DUTs and Setups for the MOSFET Model
These procedures assume that the large device is large enough to make small geometry effects irrelevant. This condition exists when the device geometries are much larger than LD and WD. For a typical process, 50*50 microns should be sufficient. To improve accuracy, enter the approximate values of LD and WD in the Parameter Editor so they can be taken into consideration in the first extraction step. A more accurate value for each is produced by the second and third extractions.
When a very large device is not available and you cannot enter LD and WD, try the following:
When only one size of device is available, extract model parameters using the following sequence. This sequence does not extract geometry dependent parameters but does extract a subset of parameters to fully model that size device.
Enter the same L and W device parameters for both DUTs. You can, if desired, reconfigure the Model so that it has only one DUT with two Setups, one similar to idvg and the other similar to idvd. Copy the first Setup from large/idvg, and the other from short/idvd. Be sure to copy complete Setups, so the appropriate extraction and optimization functions are included.
If you cannot determine the L and W for a single geometry device (as might be the case with a packaged transistor), set estimated values yourself. The actual values are less important than the ratio between them. An incorrect ratio of W/L results in extraction of an unreasonable value for UO. In general the mobility parameter, UO, should be set somewhere between 200 and 800. Start the extraction after setting the ratio of L and W to 1, then change the ratio of L to W to scale back the extracted value of UO.
P-channel MOS extractions are handled in the same way as N-channel extractions. The only difference is, you use the pmos2.mdl and pmos3.mdl Models instead of the nmos2.mdl and nmos3.mdl Models. Otherwise, the procedures are exactly as described above.
There are two capacitance extractions possible. The extraction in the cbd1/cjdarea Setup requires a single geometry to be measured and produces the parameters CJ, MJ, and PB. The extraction uses a Program Transform set_CJ to find the initial zero bias value of CJ then uses optimization to obtain all three parameter values.
The extraction in the cbd2/cjdperimeter Setup requires two geometries to be measured (one in the cbd1/cjdarea Setup and the other in the cbd2/cjdperimeter Setup) and produces the parameters CJ, MJ, PB, CJSW, and MJSW and thus a more complete capacitance model. The extractTransform uses the MOSCV_total_cap Function to simultaneously solve for the bottom area and sidewall capacitance parameters. To be able to extract the capacitance contributions from the bottom area and the sidewall periphery requires that the geometries have different area-to-perimeter ratios. The device measured with the cbd1/cjdarea Setup should have a high bottom area to perimeter area ratio and the device measured with the cbd2/cjdperimeter should have a lower bottom area to perimeter area ratio.
Place the device to be measured into the test fixture. Make sure that the CMs (Capacitance Meters Units) connected to the device correspond to the same CMs in the table of Instrument-to-Device Connections for each of the next two measurements. Be sure to calibrate the capacitance meter before taking each measurement.
The extractions of the sidewall capacitance parameter sets use the measured data from both Setups. Measure both of these Setups before executing the extraction.
Drag the pointer to Measure and release the mouse button to measure the first drain-bulk junction capacitance.
This completes the capacitance measurements.
Perform the model parameter extractions as follows:
This comp1etes the extraction of the capacitance parameters.
The instructions in previous sections showed how to execute IC-CAP commands from Setups. You can also run these same commands from a DUT. When this is done they are executed on all of the Setups in the DUT. To do so, simply move the mouse pointer on a DUT name, press LEFT, drag to one of the commands in the pop up menu and release. Since this lets you measure, extract, optimize, or simulate several Setups at a time, it is the most efficient way to operate.
Simulation of each of the Setups is performed exactly as the measurement and extractions are. Move the mouse pointer to the Setup name, press LEFT to display the pop up menu, drag the pointer to Simulate, and release the mouse button. Simulations may be performed in any order once all of the model parameters have been extracted. For further information on simulation, refer to chapter 12, Simulation.
IC-CAP provides a special function, MOSCVmodCBD, to speed up the capacitance simulation in the cbd1 and cbd2 DUTs. This function models the simple pn junction capacitance and provides a fast simulation of the CBD capacitance. To use this function to execute a simulation, specify the Transform named calc_mos_cbd_model in the Setups for the two DUTs and execute the Perform Transform command instead of the Simulate command. For further information, refer to chapter 14, Transforms and Functions.
Display Plots of measured and simulated data the same way you execute measurements, extractions, or any other IC-CAP commands. In a typical IC-CAP session, executing Plot Display from a DUT pop up menu will display all the Plots defined for the Setups in that DUT. The Plots always use the most recent set of measured and simulated data. Make sure to simulate the data after extracting parameters, but before displaying the Plot. Viewing Plots is an ideal way to compare measured and simulated data, and determining whether further optimization would be useful. For additional information on Plots, refer to chapter 15, Plots.
The optimization operation uses a numerical approach to minimize the error between measured and simulated data. As with the other IC-CAP commands, optimization may be selected at either the DUT or Setup level.
Optimization should be performed from Setups rather than from DUTs, since optimization for all Setups under a DUT is rarely required. Optimization is typically interactive in nature, with the best results obtained when you specify the characteristics of the optimization function. For further information on optimization, refer to chapter 13, Optimization.
The IC-CAP MOSFET modeling module provides a set of Setups that may be used for general measurement and model extraction for MOS devices. The IC-CAP system has the flexibility to modify any measurement or simulation specification. The model extractions provided are also intended for general MOS IC processes. If you have another method of extracting specific model parameters, IC-CAP offers the facilities to do this with the Program function or the ability to write a function in C and link it to the Function List.
All of the measurements and extractions described in the preceding sections have been performed from the Setup level. At that level, the details of the measurements are not visible. You can gain full access to, and control over, the operations of a Setup by opening the Setup window. To do so, move the mouse pointer to the desired Setup name, press LEFT and drag the pointer to the Edit command and release the mouse. The Setup window is displayed, providing access to all of the measurement and extraction specifications. For detailed instructions on modifying Setups, refer to chapter 10, Model Creation and Modification.
Typical customization includes modifying bias voltages that correspond to the performance of the device or its intended operating conditions.
The model extractions provided with IC-CAP are designed for general MOSFET processes. If a different model extraction is desired, IC-CAP provides the tools for writing them. For example, you can modify the optimization Transforms in order to optimize other model parameters. You can also use IC-CAP's Program function and Parameter Extraction Language to write tailor-made extraction Transforms. Refer to chapter 14, Transforms and Functions for more details on the Program function. For more complicated extractions, IC-CAP lets you write and compile extraction functions using the C-programming language. Writing user defined C-language routines is also explained in chapter 14, Transforms and Functions.
The following suggestions may help achieve more successful model measurements and extractions. You may incorporate some or all of these into the procedures described above.
Before starting a measurement, you can quickly verify instrument options settings. Save the current instrument option settings by saving the Model file to <your_file_name>.mdl from the Model List window. Some of the Instrument Options specify instrument calibration. For most accurate results, you must calibrate the instruments before taking IC-CAP measurements.
Make sure that the measuring instruments (specified by unit names in the Inputs and Outputs) are correctly connected to the device under test (DUT). Refer to table 5-3 for a list of nodes and corresponding measurement units. The quality of the measuring equipment (instruments, cables, test fixture, transistor sockets, and probes) can have a large effect upon the noise level in the measurements, and extracted parameter values.
For some measurements it is essential to calibrate the instruments or test hardware to remove non-device parasitics from the DUT. For MOS devices, stray capacitance due to probe systems, bond pads, and so on should be calibrated out prior to each measurement.
IC-CAP's extraction algorithms exist as functions. You can find them in the Function List, under the title Extractions. You can find the extraction Transforms for a given Setup listed in the Transform tile for the Setup.
When selecting the Extract command from the Setup level pop up menu, all extractions in the Setup are performed. Each one is executed in the same left-to-right order in which it is listed in the Setup. This order is usually critical to proper extraction performance. The extractions are typically completed in a few seconds. The newly extracted model parameter values will be placed in the Parameter Editor.
Simulation uses model parameter values currently in the Parameter Editor. A SPICE deck is created and the simulation performed. The output of the SPICE simulation is then read into IC- CAP as simulated data.
To select a simulator, use the Utilities pulldown menu in the IC-CAP Main Menu or define a SIMULATOR variable. DC simulations generally run much faster than CV simulations. The CV simulations may be done in a much shorter time by executing the calc_mos_cbd_model Transform instead of running the simulator.
If simulated results are not as expected, use the simulation debugger to examine the input and output simulation files. The debugger is listed in the Utilities menu. The output of manual simulations is not available for further processing by IC-CAP functions (such as Transforms and Plots). For detailed information on the Simulation Debugger, refer to chapter 12, Simulation.
The Display Plots function displays all graphical plots defined in a Setup. The currently active graphs are listed in the Plots tile in each Setup. After the Plot Windows are displayed, their curves are automatically updated each time a measurement or simulation is performed.
The measured data is displayed as a solid line in the Plots. Simulated data is indicated by a dashed or dotted line. After an extraction and subsequent simulation, make sure to view the Plots for agreement between the measured and simulated data.
The optimization of model parameters improves the agreement between measured and simulated data. The MOSFET model can typically be improved through the use of optimization. Optimizations are listed in the Transform tile.
An optimize Transform whose Extract Flag is set to Yes is called automatically after any extraction that precedes it in the Transform list.
This section describes the extraction algorithms for the classical, narrow width, short channel, saturation region, and sidewall capacitance extractions.
This extraction calculates the classical model parameters UO, VTO, NSUB, and UEXP from the ID versus Vg measurement at varying bulk voltages on a large device. Select the gate voltage range to cover the cutoff as well as the the linear region, including the mobility reduction range. The bulk should be biased at 0 (zero) volts as well as at values that cover the normal operating range of the device.
Parameters UO and VTO are first extracted from the Vb = 0 curve. To calculate these parameters, a least-square fit is carried out to the maximum slope of the curve in the linear region. The parameter UEXP is calculated to fit the reduction in the slope of the same curve when higher gate voltages are applied. The parameter is calculated based on the specified value of UCRIT.
The combination of UO, UEXP and UCRIT has a redundant parameter. IC-CAP keeps the UCRIT fixed at its specified value and extracts UO and UEXP. An unreasonable value for UCRIT might result in an unexpected value for the mobility UO.
The same curve fitting is carried out on the curve with the largest absolute value of bulk voltage. The threshold voltage at this bias is then calculated from the intersection of this line. The parameter NSUB is calculated from the difference in the two threshold voltages.
This extraction calculates the narrow device parameters WD and DELTA from the Id versus Vg measurement. The Setup is similar to the one described above and the extraction works in a similar manner. The threshold voltage and Beta (effective mobility) are calculated using least square fitting. The parameter WD is calculated from Beta and UO. The parameter DELTA is calculated from the shift in threshold voltage (the difference of VTH and VTO).
This extraction calculates the short channel parameters LD and XJ from the Id versus Vg measurement. The Setup is similar to the ones just described and the extraction works in a similar manner. The effective Gamma (or effective NSUB) and Beta (effective mobility) are calculated using least square fitting. The parameter LD is calculated from Beta and UO. The parameter XJ is calculated from the change in Gamma (or NSUB).
The parameter XJ is the only parameter that controls the effect of channel length on the shift of threshold voltage due to bulk bias. This parameter is extracted by IC-CAP to fit the threshold shift and therefore its extracted value may not correspond to the metallurgical junction depth. In other words, XJ is an empirical parameter in this model and not a physical parameter.
This extraction calculates the short channel parameters VMAX and NEFF from the Id versus Vd measurement. The measurement can be taken at a single gate voltage or at various gate voltages. Only the highest gate voltage curve is used in the extraction. Make sure the drain voltage sweep is sufficient to cover both the linear and saturation regions.
In this extraction, first the knee point or the saturation point is found from the shape of the curve for the maximum gate voltage. VMAX is calculated from the saturation point. The parameter NEFF is then calculated to fit the saturation portion of the curve.
To accomplish total CV extraction (due to both bottom area and sidewall area), measure two devices (DUTs), using the same Setup specifications. In these extractions, first CJ and CJSW are calculated, then PB, MJ and MJSW are extracted.
The values of CJ and CJSW are extracted from the measured capacitance data from the two different structures. The capacitors should have different ratios of their bottom area to sidewall area for best resolution of the equations. The areas and perimeters used for the calculations are stored in the Model level variable table. The example MOS Model files provided with IC-CAP use the following variable names: AreaCap1, PerimCap1, AreaCap2, and PerimCap2. The capacitor in the cjdarea Setup has a capacitance dominated by the bottom area of the device. The capacitor in the cjdperimeter Setup has a capacitance whose perimeter area contribution is significant. The names in the variable table and in the DUT must match for the extraction to perform properly.
The parameter PB is extracted using the junction capacitance measurement not dominated by the sidewall effect. This is the DUT named cbd1 in the example MOS Model files.
The total capacitance is modeled by two equations that present the bottom junction area and the sidewall junction area. The values of MJ and MJSW are obtained by simultaneously solving the two equations for total capacitance of each of the measured structures. An iterative method is used to obtain the built-in potential and grading factors.
Tables 5-5 through 5-11 list the UCB MOSFET Model Parameters by related categories, briefly describes each, and provides default values. For information on reviewing these parameters in the Circuit Editor or in the Parameter Editor, refer to chapter 3, Startup and Operation.
Name Description Default
CGBO Gate to Bulk Overlap Capacitance 0 F/m
Capacitance due to the design rules that
require the gate be extended beyond the
channel by some amount. Not voltage
dependent. Total Cgb capacitance equals
Cgbo times the channel length.
CGDO Gate to Drain Overlap Capacitance 0 F/m
Capacitance due to the lateral diffusion of
the drain in an Si gate MOSFET. Not
voltage dependent. Total Gcd capacitance
equals Cgdo times the channel width.
CGSO Gate to Source Overlap Capacitance 0 F/m
Capacitance due to the lateral diffusion of
the source in an Si gate MOSFET. Not
voltage dependent, since it is not a junction
capacitance. Total Cgs capacitance equals
Cgso times channel width.
CJSW Zero Bias Junction Sidewall Capacitance 0 F/m
Models the nonlinear junction capacitance
between the drain and the source junction
sidewall. (Pd + Ps) * CJSW = total
junction sidewall capacitance.
MJSW Grading Coefficient of Junction Sidewall 0.33
Models the grading coefficient for the
junction sidewall capacitance.
PB Bulk Junction Potential 0.8 Volt
Models the built-in potential of the bulk-
drain or bulk-source junctions. The default
is usually adequate.
FC Forward Bias Non-Ideal Junction 0.5
Capacitance Coefficient
Models the point (FC * PB) at which
junction capacitance makes the transition
between forward and reverse bias.
Table 5-5: UCB MOSFET Capacitance Parameters
Name Description Default
IS Substrate Junction Saturation Current 1x10^-16 Amp
Helps model current flow through the
bulk-source or bulk-drain junction.
JS Substrate Junction Saturation Current/m^2 1x10^-4 A/m^2
Js equals Is divided by the junction area.
For example, Isd=Js*Ad where Ad is the
drain area.
RD Drain Ohmic Resistance 0 Ohm
This parameter is geometry independent in
SPICE and IC-CAP. In fact, it is inversely
proportional to channel width.
UCRIT Critical Field for Mobility Degradation 1000 V cm^-1
Used in level=2 model only.
UEXP Critical Field Exponent 0
Used in level=2 model only.
UO Surface Mobility at Low Gate Levels 600 cm^2 /(V S)
Specifies mobility in level=2 and level=3
models. In the level=2 model, if Kp is
specified, UO will be ignored.
UTRA Transverse Field Coefficient 0
Used in level=2 model only. Set Utra to 0
to obtain same result as SPICE.
VMAX Maximum Drift Velocity of Carriers 0 m S^-1
Determines whether Vdsat is a function of
scattering velocity limited carriers or a
function of drain depletion region pinch-
off. VMAX is valid only for level=2 and
level=3 models. If VMAX is specified, the
scattering velocity limited carrier model is
used to determine Vdsat.
NEFF Total Channel Charge 1.0
A multiplicative factor of Nsub, Neff
determines saturated output conductance.
Used only in the level=2 model, and only
when Vmax is specified.
Table 5-6: UCB MOSFET Electrical Process Parameters
Name Description Default
LD Lateral Diffusion Coefficient 0 Meter
Used to determine the effective channel
length.
TOX Oxide Thickness 100 x 10^-9 Meter
Used when calculating conduction factor,
backgate bias effects, and gate-channel
capacitances.
TPG Type of Gate 1
Indicates whether gate is of metal or poly-
silicon material (0 = aluminum; 1 = opposite
substrate; -1=same as substrate). Used in
calculating threshold voltage when Vto is
not specified.
WD Channel Width Reduction 0 Meter
Used to determine the effective channel
width. This parameter is assumed to be 0 in
SPICE.
XJ Metallurgical Junction Depth 0 Meter
Defines the distance into the diffused region
around the drain or source at which the
dopant concentration becomes negligible.
Used to model some of the short channel
effects.
Table 5-7: UCB MOSFET Physical Process Parameters
Name Description Default
NFS Effective Fast Surface State Density 0 cm^-2
Used to determine subthreshold current
flow. Not valid for extracting simple linear
region classical parameters.
NSS Effective Surface Charge Density 0 cm^-2
Used to calculate threshold voltage when
Vto is not specified.
NSUB Substrate Doping Concentration 1 x 10^15 cm^-3
Used in most calculations for electrical
parameters. It is more accurate to specify
Vto rather than deriving it from Nsub.
However, Nsub should be specified when
modeling the back gate bias dependency of
Vto.
DELTA Width Effect on Threshold Voltage 0
In LEVEL=2 and LEVEL=3 models, it is
used to shift threshold voltage for different
channel widths.
ETA Static Feedback 0
Used in the LEVEL=3 model to decrease
threshold for higher drain voltage.
GAMMA Bulk Threshold 0 V^.5
The proportionality factor that defines the
threshold voltage to backgate bias
relationship. Used in the derivation of Vto,
Ids, and Vdsat. If not specified in
LEVEL=2 and LEVEL=3 models, it is
computed from Nsub.
VTO Extrapolated Zero Bias Threshold Voltage 0 Volt
Models the onset of strong inversion in the
LEVEL=1 model. Marks the point at
which the device starts conducting if weak
inversion current is ignored.
Table 5-8: UCB MOSFET Threshold Related Parameters
Name Description Default
KAPPA Saturation Field Factor 0.2
Used in the level=3 model to control
saturation output conductance.
KP Intrinsic Transconductance 0 A/V^2
If not specified for the level=2 model, KP
is computed from Kp=u0*Cox. In some of
the literature, Kp may be shown as k'. The
default for the LEVEL=1 model is 2x10e-5.
LAMBDA Channel Length Modulation 0 V^-1
Models the finite output conductance of a
MOSFET in saturation. It is equivalent to
the inverse of Early Voltage in a bipolar
transistor. Specifying this parameter
assures that a MOSFET will have a finite
output conductance when saturated. In the
level=1 model, if lambda is not specified a
zero output conductance is assumed. In the
level=2 model, if lambda is not specified,
it will be computed.
PHI Surface Potential 0 Volt
Models the surface potential at strong
inversion. If not specified in level=2 and
level=3 models, it is computed as
PHI=2kT/q *ln( Nsub/ni). PHI also may
be shown as 2*PHIb.
THETA Mobility Reduction 0 V^-1
Used in level=3 to model the degradation
of mobility due to the normal field.
Table 5-9: UCB MOSFET Electrical Parameters
Name Description Default
L Drawn or Mask Channel Length 1 x 10^-4 Meter
Physical length of the channel.
W Drawn or Mask Channel Width 1 x 10^-4 Meter
Physical width of channel.
AD Area of Drain 0 m^2
Area of drain diffusion. Used in computing
Is (from Js), and drain and source
capacitance from Cbd = CjAd.
AS Area of Source 0 m^2
Area of source diffusion. May be used as
shown in description of Ad.
NRD Equivalent Squares in Drain Diffusion 1.0
Number of equivalent squares in the drain
diffusion. Multiplied by Rsh to obtain
parasitic drain resistance (Rd).
NRS Equivalent Squares in Source Diffusion 1.0
Number of equivalent squares in the source
diffusion. Multiplied by Rsh to obtain
parasitic source resistance (Rs)
PD Drain Junction Perimeter 0 Meter
Used with Cjsw and Mjsw to model the
junction sidewall capacitance of the drain.
PS Source Junction Perimeter 0 Meter
Used with Cjsw and Mjsw to model the
junction sidewall capacitance of the source.
Table 5-10: UCB MOSFET Device Geometry Parameters
Name Description Default
LEVEL Extraction Level 1
Specifies one of four extraction levels. If
not specified, defaults to LEVEL 1.
Table 5-11: UCB MOSFET General Parameters
The general form of the Ids equation for the HSPICE LEVEL 6 MOSFET model is similar to the UCB MOS LEVEL 2 model. However, small geometry effects such as mobility reduction and channel length modulation are modeled differently. Also, the LEVEL 6 model can be used for modeling MOS transistors with ion-implanted channels due to its multi-level GAMMA capability. The HSPICE MOS LEVEL 6 model is based on the ASPEC, MSINC, and ISPICE MOSFET model equations and has been enhanced by Meta-Software. Different versions of the model are invoked with the switch parameter UPDATE. In addition, there are more than 5 other switch parameters which are used for selecting different model equations. Refer to the HSPICE User's Manual [2] for detailed information on this model.
The IC-CAP LEVEL 6 model parameter extraction routines and configuration file are described in this section. Three extraction functions for this model are included in the IC-CAP function library. The configuration file, hnmos6.mdl, supports a limited number and combination of parameters in the LEVEL 6 model. However, different parameter combinations can be supported by modifying the included optimization strategy. This configuration file can also be used for the HSPICE MOS LEVEL 7 model, provided that the PHI parameter is set to PHI/2 following the extraction.
NOTE: Make sure to set the SIMULATOR variable to your version of HSPICE after loading the hnmos6.mdl configuration file into the IC-CAP. Referto chapter 12, Simulation, for additional details on using HSPICE.
The parameters used in the hnmos6.mdl configuration file are shown in Table 5-12. Six switch parameters are selected in the supplied configuration. The fixed parameter values are based on typical MOSFETs. Therefore, they may need to be altered for certain devices. Refer to the HSPICE User's Manual for additional information.
Switch Parameters Fixed Parameters Extracted Parameters
UPDATE=1 BULK=99 KU
ACM=0 FDS=0.9 MAL
CAPOP=4 LATD=0.2 MBL
MOB=1 ESAT=86.0E3 PHI
CLM=3 KL=0.05 VT
WIC=1 KA=0.97 GAMMA
VSH=0.7 LGAMMA (Optional)
KCL=1.0 VBO (Optional)
MCL=1.0 F1
LAMBDA
UB
TOX (Input Parameter) F3
L (Input Parameter) NFS
W (Input Parameter) LD or LDEL
WD or WDEL
RD
RS
XJ
DELTA
NWM
SCM
CJ
MJ
PB
CJSW
MJSW
Table 5-12: HSPICE LEVEL 6 Parameters used in hnmos6.mdl
An important feature of the HSPICE LEVEL 6 model is its multi-level Gamma capability. The IC-CAP extraction routines support both single and multi level Gamma parameters extractions. If VBO is set to 0 before the Large IdVg extraction, only GAMMA is extracted. Otherwise, GAMMA, LGAMMA, and VBO are extracted. Optimization is necessary with the LEVEL 6 model for optimum agreement between measured and simulated data.
The IC-CAP Setup attributes for the LEVEL 6 model are shown in table 5-13.
DUT SETUP INPUTS OUTPUTS TRANSFORM FUNCTION EXTRACTIONS
large idvg vg,vb,vd,vs id extract MOSDC_lev6_lin_large PHI,VT,GAMMA,LGAMMA,VBO,
LAMBDA,UB,NFS
optimize Optimize PHI,VT,GAMMA,LGAMMA,VBO,
F1,F3
opt_NFS Optimize NFS
narrow idvg // // extract MOSDC_lev6_lin_narrow NWM,WD(EL),DELTA
optimize Optimize NWM,WDEL
short idvg // // extract MOSDC_lev6_lin_short SCM,XJ,LD(EL)
optimize Optimize SCM,XJ,LDEL,RD,RS
short idvd vd,vg,vb,vs id optimize Optimize KU,MAL,LAMBDA,MBL
cbd1 cjdarea vb,vd cbd set_CJ Program initial zero bias CJ
extract Optimize CJ,MJ,PB
cbd2 cjdperimeter vb,vd cbd extract MOSCV_total_cap CJ,MJ,CJSW,MJSW,PB
Table 5-13: Setup Attributes for the LEVEL 6 Model
The measurement Setups are identical to the UCB MOS LEVEL 2 and LEVEL 3 model configuration files. However, to get accurate GAMMA and LGAMMA parameters for ion-implanted devices, the measured data needs to clearly express the body effects. Therefore, the bulk voltage should be set broadly on the Large IdVg measurement. The following sequence for DC measurements is recommended:
All DC parameters are extracted and optimized with the DCExtraction Macro. Alternately, extractions and optimizations can be performed interactively as described for the LEVEL 2 and LEVEL 3 MOSFET models. There is no extraction routine in the short IdVd Setup for saturation region parameters. Instead, the parameters KU, MAL, MBL, and LAMBDA must be optimized. For certain devices it may be necessary to alter the optimization setup and default parameter values for accurate results.